There are several circumstances in the digital manipulation of numbers where it is required to perform an addition of two binary numbers and then decode the result. The term decode is used herein to denote the selection of a particular preset output value in dependence on the result of the addition. For example, the digital execution of long division involves a cycle of subtracting from a remainder REM held in register A a value M held in register B which is a whole multiple of the divisor D. In terms of hardware, the subtraction is performed in an adder by inverting the value M and adding the inverted value -M to the remainder REM. The result X of the addition is passed to a look up table which decodes the result by comparing it with each of a plurality of integers (1-100) to determine a "match". The new value M stored against the matched value is then output to perform the next addition step. The result X becomes the next remainder REM for the subsequent cycle. This procedure is shown diagrammatically in FIG. 1.
In another example, a computer program frequently requires the loading of an instruction to a particular register which is identified in relation to a base register by an (x+r)-type instruction in the program, where r is the location of the base register and x the number to be added thereto to determine the location of the particular register. Firstly the addition (x+r) must be performed and then the result of the addition must be supplied to a look up table to determine the output value associated with the result of the addition.
The execution of an addition followed by a decoding operation is costly in terms of time. It is an object of the present invention to increase the speed at which such operations can be executed and thereby improve the efficiency of processes using these steps.